1. Field of the Invention
The present invention relates to the field of integrated circuits manufacturing technology. More particularly, the invention relates to a method for fabrication of shallow trench isolation whereby corner erosion of shallow trench isolation is avoided and the performance of the semiconductor device is thereby improved.
2. Description of the Related Art
Filling the shallow trench in the semiconductor substrate with insulating materials, such as silicon dioxide, by high density plasma-chemical vapor deposition (HDPCVD) to form shallow trench isolation (STI) has gradually replaced the conventional Local Oxidation of Silicon (LOCOS) method to become the major method of active region isolation. The method of fabricating STI in the prior art, in general, consists of defining the shallow trench first by removing part of the pad layer and semiconductor substrate after the pad layer is formed on the semiconductor substrate. Second, xe2x80x9cpull-backxe2x80x9d is performed on the pad layer to xe2x80x9cpull backxe2x80x9d the pad layer and expose part of the surface of the semiconductor substrate and its corner formed with the opening of the shallow trench. Thermal oxide film and nitride liner film are sequentially formed to cover the surface of the semiconductor substrate and the inner walls of the shallow trench. However, because of corner thinning, the thickness of the thermal oxide film formed on the corner is thinner than that formed on the surface of the semiconductor substrate or the inner walls of the shallow trench. Then the shallow trench is filled with insulating materials, such as silicon dioxide, by high-density plasma-chemical vapor deposition (HDPCVD) and so on. Then the exposed thermal oxide film and the nitride liner film are sequentially removed by isotropic etching. The rest of the thermal oxide film and the silicon nitride pad thin film are over-etched to expose the opening of the shallow trench and the corner of the surface of the semiconductor substrate. Later, after forming the gate oxide and the gate on the surface of the semiconductor substrate, current leakage is likely to occur in the gate oxide on the corner because of corner thinning. Thus the reliability of the gate is lowered, and the performance of the metal oxide semiconductor transistors is affected. The following refers to FIG. 1A to FIG. 1F showing a cross-section of STI fabrication to describe the process thereof.
In FIG. 1A, a semiconductor substrate 100 is provided. A pad layer 105 with a pad silicon oxide layer 102 and a pad silicon nitride layer 104 is formed on the surface of the silicon substrate 100. Next, part of the pad layer 105 is removed to define an opening (not shown), then pad layer 105 is used as a mask to perform isotropic etching to form shallow trenches 106 in the semiconductor substrate 100. Next, xe2x80x9cpull-backxe2x80x9d is performed on the pad layer 105: an anisotropic etching is performed to remove part of the pad layer 105 around the opening of shallow trenches 106, then part of the surface of the semiconductor substrate and its corner 107 between the opening of shallow trenches are exposed.
Next, in FIG. 1B, a thermal oxide film 110 is formed on the inner walls of the shallow trenches 106 and the exposed surface of the semiconductor substrate 100 by thermal oxidation. Because of corner thinning, the thickness of the thermal oxide film 110 on the inner walls of the shallow trenches 106 and the exposed surface of the semiconductor substrate 100 is greater than that on the corner 107.
In FIG. 1C, pad silicon oxide layer 102 and thermal oxide film 110 are shown as a first oxide layer 112 for convenience of explanation. A nitride liner film 120 is deposited by CVD to cover the sidewalls of the pad silicon nitride layer 140 and the surface of the first oxide layer 112 in the shallow trenches 106.
Next, in FIG. 1D, an insulating layer (not shown) of, for example, high-density plasma oxide (HDP Oxide), is formed to fill up the shallow trenches 106. Then, part of the insulating layer is removed by a Deglaze step using HF-type etching agents to form a first opening 108. The rest of the insulating layer is represented as insulating layer 130. The insulating layer 130 is divided into the top part 134 and the bottom part 132, because the top part 134 is formed in the space surrounded by the xe2x80x9cpulled-backxe2x80x9d pad layer 105, thus its width is greater than the bottom part 132.
In FIG. 1E, anisotropic etching is performed to remove the pad silicon nitride layer 104 and part of the nitride liner film 120, thus the top part of the insulating layer 134 and its sidewalls and part of the first oxide layer 112 are exposed. Furthermore, part of the nitride liner film 120 under the top part of the insulating layer 134 is over-etched, thus the second opening 124 is formed. The rest of the nitride liner film 120 is represented as the rest of the nitride liner film 120xe2x80x2.
Next, in FIG. 1F, the first oxide layer 112 not covered with the rest of the nitride liner film 120xe2x80x2 is removed by isotropic etching, thus the surface of the semiconductor substrate 100 is exposed. Furthermore, part of the first oxide layer 112 under the top part of the insulating layer 134 and the rest of the nitride liner film 120xe2x80x2 is over-etched, thus the corner 107 is exposed and the third opening 142 is formed. The rest of the first oxide layer 112 is represented as the rest of the first oxide layer 112xe2x80x2. So far the conventional steps of fabricating STI are completed.
According to the conventional process, the corner is exposed after the pad oxide layer on the semiconductor substrate is removed. Later in the semiconductor manufacturing process, after the gate oxide and the gate are formed on the semiconductor substrate, current leakage is likely to occur at the gate oxide formed on the corner because of corner thinning. Thus the reliability of the gate is lowered, and the performance of the metal oxide semiconductor transistor is affected.
Therefore, the purpose of the invention is to provide a method of fabricating STI, in which a refill step of oxide layer and a step of forming a sacrificial layer on the semiconductor substrate are applied after filling an insulating layer into the shallow trenches. The purpose of the steps is to protect the oxide layer on the semiconductor substrate and the corner of the shallow trenches, used to isolate the STI.
Thus, the invention provides a method of fabricating shallow trench isolation on a semiconductor substrate, comprising: forming a pad layer on the semiconductor substrate; removing part of the pad layer to form an opening, then using the pad layer as mask to define a shallow trench in the semiconductor substrate; removing part of the pad layer around the opening of the shallow trenches to expose the surface of the semiconductor substrate thereunder and form a corner between the surface of the semiconductor substrate and the opening of the shallow trenches; forming a thermal oxide film on the surface of the semiconductor substrate exposed in the sidewalls of the shallow trenches to constitute a first oxide layer with the pad layer; forming a nitride liner film to cover the surface of the first oxide layer on the sidewalls of the shallow trenches and the pad layer on the opening of the shallow trenches; forming an insulating layer to fill the shallow trenches; forming a first opening by removing part of the insulating layer in the shallow trenches, such that the rest of the insulating layer is divided into top and bottom parts; removing the pad silicon nitride layer and the nitride liner film not covered with the top part of the insulating layer to expose the top part of the insulating layer, its sidewalls and part of the first oxide layer, such that the nitride liner film under the top part of the insulating layer is over-etched to form a second opening; forming a second oxide layer to cover the upper surface of the top part of the insulating layer and the surface of the first oxide layer exposed at the sidewalls of the top part of the insulating layer, and to fill the second opening; removing the second oxide layer and the first oxide layer not covered with the top part of the insulating layer and the surface of the semiconductor substrate is exposed, wherein part of the first oxide layer under the top part of the insulating layer is removed by over-etching, thus the third opening is formed; forming a sacrificial oxide layer on the exposed semiconductor substrate such that part of the third opening is filled to constitute a third oxide layer with the rest of the first oxide layer; forming a fourth oxide layer to cover the upper surface of the top part of the insulating layer, its sidewalls and the surface of the third oxide layer, and to fill the third opening; and removing the fourth oxide layer and part of the third oxide layer such that the upper surface of the top part of the insulating layer, its sidewalls, and the surface of the semiconductor substrate are exposed to form a shallow trench isolation comprising the top part and the bottom part of the insulating layer.
According to the preferred embodiment of the present invention, the semiconductor substrate is silicon or germanium. The substrate is formed by Epitaxy or silicon-on insulating materials. The insulating layer, the second oxide layer and the third oxide layer are all boron-phosphorous-silicon glass (BPSG), non-doping silicon glass (NSG), high-density plasma (HDP) oxide, or tetraethylethoxide (TEOS) by chemical vapor deposition (CVD), atmospheric-pressure CVD (APCVD), sub-atmospheric-pressure CVD (SAPCVD), low-pressure CVD (LPCVD), plasma-enhanced CVD (PECVD), or high-density plasma CVD (HDPCVD).